This invention relates to a routing system for use in connecting a plurality of input lines to a plurality of output lines.
A conventional routing system of the type described is used for transferring an asynchronous transfer mode (ATM) cell from a selected one of input lines to one or ones of output lines. To this end, the routing system comprises an ATM switch network having a plurality of input ports, a plurality of output ports, a switch circuit between the input and the output ports, and a switch control section for controlling the switch circuit. More particularly, the switch circuit is operable to form internal paths between the input and the output ports under control of the switch control section. The switch circuit comprises a plurality of switch units divided into a plurality of stages, namely, a multistage of switch units and buffers which correspond to the input ports, the output ports, or the like. The buffers serve to hold the ATM cells received at random and to avoid congestion of the ATM cells destined to a single one of the input ports or the output ports.
Furthermore, the routing system comprises an input section located between the input lines and both the switch circuit and the switch control section and an output section located between the output lines and the switch circuit.
Such a routing system is designed so that probability of collision among ATM cells becomes as small as possible and is practically reduced, for example, to 10.sup.-10. However, when serious congestion takes place among the ATM cells, the collision among the ATM cells might occur even when the probability is very low. Occurrence of the collision brings about selective abandonment or discard of the ATM cell or cells due to an overflow of each buffer. This shows that the discarded ATM cell is not transmitted to the output lines. Therefore, such occurrence of collision of ATM cells should always be detected to analyze the cause of occurrence of the discarded ATM cell. Otherwise, abandonment or discard of the ATM cell might frequently and unfavorably take place in the routing system.
In order to detect the collision of the ATM cells, each of the buffers is monitored by a counter which counts the discarded ATM cells resulting from the overflow of each buffer.
With this structure, the discarded ATM cells can be detected in number by monitoring the counts of the counters. However, it is impossible to detect input port numbers concerned with the discarded ATM cells, a routing information signal, such as the output port number, and a header or a header information signal, such as a virtual path identifier (VPI), a virtual channel identifier (VCI). This makes it difficult to analyze the cause of occurrence of the discarded ATM cells.
In another conventional routing system, a plurality of external input cells each of which usually has a cell length of fifty-three (53) bytes are multiplexed by an input section into an internal multiplexed input cell sequence which is sent to a switch circuit through each of input ports of the ATM switch network. On the other hand, each internal multiplexed input cell sequence is separated by an output section into a plurality of external output cells sent through the output lines.
Herein, it is to be noted that the internal multiplexed input cell sequence is delivered to the switch circuit at a rate higher than that of the external input cells and that the switch circuit should be operated at a high speed. Such a high speed operation is not always desirable for the switch circuit.
Taking this into consideration, attention is directed to parallel processing of bits of each cell of the internal multiplexed input cell sequence in the switch circuit. However, such parallel processing is practically difficult because the byte number of fifty-three (53) included in each cell is a prime number. Specifically, if a switch unit is assigned to each bit of the cell, this requires the use of the switch units of 53.times.8, namely, 424 so as to carry out the parallel processing at every stage.
Under the circumstances, the cell length of 53 bytes is converted into a converted cell length of, for example, 54 bytes, 56 bytes, or 64 bytes. This shows an empty field is left in a converted cell having the converted cell length. Such conversion of cell lengths facilitates parallel processing and makes it possible to reduce an amount of hardware because the switch units can be reduced in number, as known in the art.
In general, a routing information signal of a multistage switch is located in the empty field of the converted cell. Thus, if the routing information signal is located in the empty field, an amount of routing information is unpleasingly increased as a size of the switch circuit becomes large. Therefore, the converted cell length should be determined in dependency upon an amount of information carried by the routing information signal. This makes it difficult to cope with change or expansion of a size of the switch network.
On the other hand, proposal is made about transferring the routing information signal through a different signal line and another switch circuit different from the switching circuit for transfer of each cell. However, necessity of the different signal line and the different switch circuit makes a size of hardware objectionably large.
At any rate, the above-mentioned processing of each input cell is not always optimum in each conventional routing system so as to analyze the discarded cell and to transmit the routing information signal. This is because the routing information signal is not effectively used in the conventional routing systems.